CN201004686Y

CN201004686Y - Video signal synthesis controller

Info

Publication number: CN201004686Y
Application number: CNU2006200165698U
Authority: CN
Inventors: 梁宁
Original assignee: Konka Group Co Ltd
Current assignee: Konka Group Co Ltd
Priority date: 2006-12-19
Filing date: 2006-12-19
Publication date: 2008-01-09
Anticipated expiration: 2016-12-19

Abstract

The utility model discloses a multi channel digital video signals compounding method belonging to digital video signals processing technical field, which is aimed to enhance the anti jamming functions and stability of the signal source when a video signal channel is plugged into a HD RGB display device. the utility model comprises and is characterized in that: a crystal oscillator, and a CLK producing system clock signal. A HD synchronous signal generating circuit controlled by the CLK produces HD synchronous signals, and send out the signals in two channels; one channel is sent to the RGB display device, another is sent to the memory controller, producing DEN signals and data groups; the DEN signals is delivered into the switch and buffering circuit, and then RGB video data is output to the HD RGB display device. The utility model has the advantages in that: strong anti jamming performance; enhanced stability of signal source; single pixel processing unit without adding noise points meeting HD display requirements; independent working without computer quick running at starting up.

Description

The vision signal synthetic controller

Technical field

It is synthetic to the utility model discloses a kind of multi-channel video signal synthesizer, particularly digital video signal, belongs to the digital video signal processing technology field.

Background technology

Video monitoring system is widely used in occasions such as urban transportation, electric power, colliery, telecommunications, public security 110 and Military Application.In video monitoring system, usually adopt the vision signal synthetic controller, on high-resolution RGB display device, show multi-channel video signal with full frame or multiwindow pattern, conventional vision signal synthetic controller is based on the traditional control system of " computer+integrated circuit board " mode of Windows operating system mostly, poor stability, and can not divorced from computer and independent operating.As Chinese patent " four picture segmentation numerals are looked and made frequency processing device picture segmentation device for processing digital video ", disclosed is one four picture segmentation digital video-processing unit DRAM, synthetic each circuit-switched data of storage.Obtain every way word video data in the single game mode, four picture horizontal resolutions are dwindled one times be the CIF form, synthesize a standard digital vedio data again.

The utility model content

At above-mentioned analysis, the utility model is different with the prior art solution.Its objective is that signal is synthetic in the solution channel video signal access high definition RGB display device process, main circuit is based on programmable logic device (FPGA) and Embedded System Design.The antijamming capability in enhancing signal source and stability, but divorced from computer independent operating.

Realizing of task of the present utility model by following design: the vision signal synthetic controller, comprise vision signal treatment channel and high definition RGB display device, its technical characterictic is:

Crystal oscillator produces clock signal of system CLK;

Based on FPGA design high definition circuit for generating synchronous signals, controlled by system clock CLK, produce the high definition synchronizing signal: field sync signal Vsync, line synchronizing signal Hsync, and data useful signal DEN and data clock signal DCLK.

The high definition circuit for generating synchronous signals, the Vsync of output, Hsync, DCLK and DEN signal are sent into storage control, and another group Vsync, Hsync, DCLK directly are sent to high definition RGB display device.

Storage control, at sets of signals Vsync, Hsync, DCLK and DEN, and system clock CLK control according to the requirement of many windows display format, produces the storage control signal of each memory cell down.

Storage control signal is relevant with the memory cell chip that is adopted, and generally is divided into two big classes: address bus signal and read-write control signal.

Switch and buffer circuit, under memory controller controls,, switch the vedio data RGB that sends respective memory unit and arrive high definition RGB display device with an epideictic behaviour unit.The sprite intersection makes the data set of output get null value, thereby produces the black surround septal line, makes the sprite sharpness of border as seen.

The good effect that the utility model produces is remarkable, owing to adopt programmable logic device FPGA and embedded design, circuit structure is more optimized, and it is strong to have an antijamming capability, and signal source stability is high; With single pixel serves as to handle unit, to picture material without any infringement, can appended drawings as noise, satisfy the high definition display requirement fully; But divorced from computer independent operating, start are quick operate as normal.

Description of drawings

Fig. 1, be the utility model vision signal synthetic controller schematic diagram.

Fig. 2, be that the high definition of a certain form of the utility model is synchronous, data effectively reach clock signal waveform schematic diagram.

Fig. 3, be a kind of 4 window scheme display format figure vision signal synthetic controller schematic diagrames of the utility model.

See Fig. 1, synthesize example with 4 tunnel vision signals, circuit is made up of vision signal treatment channel 1～4, crystal oscillator 5, high definition circuit for generating synchronous signals 6, storage control 7 and switching and buffer circuit 8.Expression prior art in the frame of broken lines.The operation principle of each road vision signal treatment channel is identical.Form by video signal source a, decoding convergent-divergent circuit b and memory cell c.For the analog video signal source, after needing decoding circuit to convert digital video signal to, send into the convergent-divergent circuit and carry out convergent-divergent, then need not decoding for digital video signal source, directly send into the convergent-divergent circuit and carry out convergent-divergent, the digital video signal that produces behind the convergent-divergent under storage control 7 controls, deposits corresponding memory cell c in.Video signal source a, decoding convergent-divergent circuit b and memory cell c belong to prior art, are omitted herein.

Crystal oscillator 5, the clock signal of system CLK of generation whole video synthetic controller, its frequency can be taken as the operating frequency of memory cell, as 100MHz, 120MHz, 133MHz or 166MHz, decides on memory cell.

High definition circuit for generating synchronous signals 6, design based on FPGA, it produces the high definition synchronizing signal of certain format: field sync signal Vsync, line synchronizing signal Hsync, and data useful signal DEN and data clock signal DCLK under system clock CLK control.

By Vsync, Hsync, DCLK and the DEN signal of high definition circuit for generating synchronous signals 5 outputs, send into storage control 7 for one group, another group (Vsync, Hsync, DCLK) directly is sent to high definition RGB display device.

Storage control is at sets of signals Vsync, Hsync, DCLK and DEN, and system clock CLK control according to the requirement of many windows display format, produces the storage control signal of each memory cell down.Storage control signal is relevant with the memory cell chip that is adopted, and generally is divided into two big classes: address bus signal and read-write control signal.

Switch and buffer circuit 8, under storage control 7 controls,, switch the vedio data RGB that sends respective memory unit and arrive high definition RGB display device with an epideictic behaviour unit.Be data useful signal DATAEN after the DEN signal suitably postponed, high definition RGB display device is sent in output.

Fig. 2 has provided that the high definition of a certain form is synchronous, data effectively reach the clock signal waveforms, field signal Vsync and field duration, row signal Hsync and line period, data useful signal DEN and data clock signal DCLK.

Most preferred embodiment

Fig. 3 is the utility model most preferred embodiment figure, supposes 4 window scheme display formats, and full frame is that R1+R2 is capable, and C1+C2 row, picture 1 account for the capable C1 row of R1, corresponding to frame of broken lines Fig. 1 video signal source in the upper left corner; Picture 2 accounts for the capable C2 row of R1, corresponding to frame of broken lines Fig. 2 video signal source in the upper right corner; Picture 3 accounts for the capable C1 row of R2, corresponding to frame of broken lines Fig. 3 video signal source in the lower left corner; Picture 4 accounts for the capable C2 row of R2, corresponding to frame of broken lines Fig. 4 video signal source in the lower right corner.The horizontal direction dotted line is represented respectively: the 1st row, the 2nd row, and R1 is capable, R1+1 is capable, and R1+R2 is capable.Perpendicular dotted line is represented respectively: the 1st row, C1 row, C1+1 row, C1+C2 row.

Picture 1 is the capable and C1 row of R1, and picture 2 is the capable and C2 row of R1, and picture 3 is the capable and C1 row of R2, and picture 4 is the capable and C2 row of R2.

R1 and R2 are integer, its value the full screen display total line number 1/3 to 2/3 between, C1 and C2 are integer, its value the full screen display total columns 1/3 to 2/3 between, too small integer value can influence the effect of convergent-divergent circuit.

The situation of cutting apart according to display frame, the capable C1 row of convergent-divergent circuit output R1 view data in the channel video signal 1, the capable C2 row of convergent-divergent circuit output R1 view data in the channel video signal 2, the capable C1 row of convergent-divergent circuit output R2 view data in the channel video signal 3, the capable C2 row of the convergent-divergent circuit output R2 view data in the channel video signal 4.

When showing the 1st row, at the 1st to C1 row, commutation circuit is sent memory cell the 1st row view data in the passage 1, and to the C1+C2 row, commutation circuit is sent memory cell the 1st row view data in the passage 2 at C1+1; When showing the 2nd row, at the 1st to C1 row, commutation circuit is sent memory cell the 2nd row view data in the passage 1, and to the C1+C2 row, commutation circuit is sent memory cell in the passage 2 at C1+1

The 2nd row view data; , the rest may be inferred.

When showing that R1+1 is capable, at the 1st to C1 row, commutation circuit is sent the capable view data of memory cell R1+1 in the passage 3, and to the C1+C2 row, commutation circuit is sent the capable view data of memory cell R1+1 in the passage 4 at C1+1; When showing that R1+2 is capable, at the 1st to C1 row, commutation circuit is sent the capable view data of memory cell R1+2 in the passage 3, and to the C1+C2 row, commutation circuit is sent the capable view data of memory cell R1+2 in the passage 4 at C1+1; , the rest may be inferred.

As can be seen, video signal source is behind decoding convergent-divergent circuit, the output digital image signal, to treatment of picture is to be the digital processing process of unit with the pixel, to picture material without any infringement, can appended drawings as noise, picture quality depends on decoding convergent-divergent circuit fully, decoding convergent-divergent circuit adopts the application-specific integrated circuit (ASIC) of technology maturation.

As producing the black surround septal line between sprite, only need when the ranks of handling the septal line correspondence are counted, to force that view data is got null value and get final product.There are abundant trigger and I/O pin in FPGA inside.By leave in program in the ram in slice its operating state is set, therefore, need the RAM in the sheet be programmed during work.

More than exemplified the synthetic of 4 passage vision signals, for synthesizing of other port number vision signal, principle is identical, no longer applies and states.

Claims

1, a kind of vision signal synthetic controller comprises vision signal treatment channel and high definition RGB display device, and its technical characterictic is:

Crystal oscillator produces clock signal of system CLK;

The high definition circuit for generating synchronous signals is controlled by system clock CLK, produces the high definition synchronizing signal and divides two-way to send, and one the road to high definition RGB display device; Another road is sent into

Storage control produces DEN signal and data set; The DEN signal is sent into

Switch and buffer circuit, output video image data RGB is to high definition RGB display device.

2, a kind of vision signal synthetic controller according to claim 1, its technical characterictic is:

The high definition circuit for generating synchronous signals, based on the FPGA design, it produces the high definition synchronizing signal of certain format: field sync signal Vsync, line synchronizing signal Hsync, and data useful signal DEN and data clock signal DCLK under system clock CLK control.

3, a kind of vision signal synthetic controller according to claim 1 and 2, its technical characterictic is:

Said high definition circuit for generating synchronous signals is sent one group of Vsync, Hsync, DCLK and DEN signal to storage control, and another group Vsync, Hsync, DCLK directly deliver to high definition RGB display device.

4, according to the described a kind of vision signal synthetic controller of claim 1, its technical characterictic is: said storage control, and at sets of signals Vsync, Hsync, DCLK and DEN, and system clock CLK control is down, according to the requirement of many windows display format, produce storage control.

5, according to the described a kind of vision signal synthetic controller of claim 1, its technical characterictic is the storage control that is right, and the storage control signal that sets of signals and system clock control produce down is divided into two class address bus signal and read-write control signal.

6, according to the described a kind of vision signal synthetic controller of claim 1, its technical characterictic is: said depositing switched the storage controller, under memory controller controls, with an epideictic behaviour unit, switch and send respective memory unit, switch the vedio data RGB that sends respective memory unit and arrive high definition RGB display device.

7, according to the described a kind of vision signal synthetic controller of claim 6, its technical characterictic is: said depositing switched the storage controller, and the data useful signal DATAEN after the DEN signal is postponed is sent to high definition RGB display device.

8, according to the described a kind of vision signal synthetic controller of claim 1, its technical characterictic is: said depositing switched the storage controller, makes the data set of output get null value at the sprite intersection, thereby produces the black surround septal line, makes the sprite sharpness of border as seen.

9, according to the described a kind of vision signal synthetic controller of claim 2, its technical characterictic is: said crystal oscillator, produce whole clock signal of system CLK, its frequency can be taken as the operating frequency of memory cell, is 100MHz, 120MHz, 133MHz or 166MHz.